Design and Analysis of a 2D Vernier Structure

Abstract

This paper presents the design and simulation of a 2D Vernier Time-to-Digital Converter (TDC) targeting less than 20 picosecond time resolution and 5-bit output resolution. The TDC comprises voltage-controlled delay buffers, NAND-based SR latches with reset functionality, and a calibration loop using a phase-frequency detector (PFD) and charge pump. The calibration loop dynamically adjusts delay mismatches to maintain consistent timing across process-voltage-temperature (PVT) corners, significantly improving linearity. Simulations show that the TDC achieves a resolution of 16.9 ps for tt corner and maintains DNL and INL below 0.5 LSB under all tested PVT conditions